Creating a Packet Processing application using the VC709(Virtex) platform

  • Import packet matching engine to the FPGA (vc709) context. Source found in $(VSI_INSTALL)/target/common/hls_examples/regex_packet/match/regex_exec.cc
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  • Import Match Compiler to the Software (X86) context. Source found in $(VSI_INSTALL)/target/common/hls_exmples/regex_packet/compile/regex_comp.cc
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  • Add a TCP server to Softwar (X86) Context that will feed the pattern to be compiled and sent the matching engine. Set the server port to 2020
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  • Add another TCP server in X86 that will send the packets to the line and recive matched packets back. Set the server port to 2021
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  • Annotate connections to be traced
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  • Generate the complete system & hardware
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  • Synthesize the pattern matching engine using Vivado HLS
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  • Compile the Software project
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  • Generate FPGA bitstream for the FPGA project
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