Creating the Sort Demo

• Import C/C++ code into VSI system Canvas (Using sort.cc which is can be found at $VSI_INSTALL/target/common/sort)

• Add the TCP Server software IP block to the Software Context from IP Library

• At this point you have a complete software project to perform sort in software
  • Flow –> Generate System …

• Next we move the sort block from software to hardware

• Add Trace to interfaces of interest
  • Right Click “Toggle Trace..”

• Generate the complete software , hardware & HLS projects
  • Flow –> Generate System …

• Use HLS to convert sort function to verilog

• Compile Software Project created for Zynq_PS